MC68HC908GP20 Datasheet, PDF (125/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

• PLL VCO range select register (PMRS)
(See 7.6.5 PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS)
(See 7.6.6 PLL Reference Divider Select Register.)
Figure 7-3 is a summary of the CGMC registers.
Addr. Register Name
Bit 7
6
5
4
$0036
Read:
PLLF
PLL Control Register
(PCTL)
Write:
PLLIE
PLLON BCS
Reset: 0
0
1
0
Read:
LOCK
0
$0037
PLL Bandwidth Control
Register (PBWC)
Write:
AUTO
ACQ
Reset: 0
0
0
0
Read: 0
0
0
0
$0038
PLL Multiplier Select High
Register (PMSH)
Write:
Reset: 0
0
0
0
Read:
$0039
PLL Multiplier Select Low
Register (PMSL)
Write:
Reset:
MUL7
0
MUL6
1
MUL5
0
MUL4
0
$003A
Read:
PLL VCO Select Range
Register (PMRS)
Write:
Reset:
VRS7
0
VRS6
1
VRS5
0
VRS4
0
Read: 0
0
0
0
$003B
PLL Reference Divider
Select Register (PMDS)
Write:
Reset: 0
0
0
0
= Unimplemented
R
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
3
PRE1
0
0
2
PRE0
0
0
0
0
MUL11 MUL10
0
0
MUL3 MUL2
0
0
VRS3 VRS2
0
0
RDS3 RDS2
0
0
= Reserved
Figure 7-3. CGMC I/O Register Summary
1
VPR1
0
0
0
MUL9
0
MUL1
0
VRS1
0
RDS1
0
Bit 0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
RDS0
1
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
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