MC68HC908GP20 Datasheet, PDF (27/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

List of Figures
Figure
Title
Page
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . 315
SPI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 316
Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . 317
Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . 321
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . 322
Transmission Start Delay (Master). . . . . . . . . . . . . . . . . . . 324
SPRF/SPTE CPU Interrupt Timing. . . . . . . . . . . . . . . . . . . 325
Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . 327
Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . 328
SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . 331
CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . 338
SPI Status and Control Register (SPSCR). . . . . . . . . . . . . 340
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . 343
21-1
21-2
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
22-9
22-10
22-11
22-12
22-13
22-14
22-15
22-16
22-17
Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . . 347
TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . 355
PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . 360
TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . 366
TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . 368
TIM Counter Registers Low (TCNTL). . . . . . . . . . . . . . . . . 368
TIM Counter Modulo Register High (TMODH) . . . . . . . . . . 369
TIM Counter Modulo Register Low (TMODL). . . . . . . . . . . 369
TIM Counter Register High (TCNTH) . . . . . . . . . . . . . . . . 370
TIM Counter Register Low (TCNTL) . . . . . . . . . . . . . . . . . 370
TIM Channel 0 Status and Control Register (TSC0) . . . . . 371
TIM Channel 1Status and Control Register (TSC1) . . . . . . 371
CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . 376
TIM Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . . . . 376
TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . 376
TIM Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . . . . 376
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
27