MC68HC908GP20 Datasheet, PDF (105/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

6.6.3 Break Status Register
The break status register (SBSR) contains a flag to indicate that a break
caused an exit from wait mode. The flag is useful in applications
requiring a return to wait mode after exiting from a break interrupt.
Address: $FE00
Bit 7
6
5
4
3
Read: 0
0
0
1
0
Write: R
R
R
R
R
Reset: 0
0
0
1
0
Note: Writing a logic 0 clears BW. R = Reserved
2
1
Bit 0
0
BW
0
R
NOTE
R
0
0
0
Figure 6-6. SIM Break Status Register (SBSR)
BW — Break Wait Bit
This read/write bit is set when a break interrupt causes an exit from
wait mode. Clear BW by writing a logic 0 to it. Reset clears BW.
1 = Break interrupt during wait mode
0 = No break interrupt during wait mode
BW can be read within the break interrupt routine. The user can modify
the return address on the stack by subtracting 1 from it. The following
code is an example.
This code works if the H register was stacked in the break interrupt
routine. Execute this code at the end of the break interrupt routine.
HIBYTE
LOBYTE
;
DOLO
RETURN
EQU 5
EQU 6
If not BW, do RTI
BRCLR BW,BSR, RETURN
TST
BNE
DEC
DEC
PULH
RTI
LOBYTE,SP
DOLO
HIBYTE,SP
LOBYTE,SP
; See if wait mode or stop mode
; was exited by break.
; If RETURNLO is not 0,
; then just decrement low byte.
; Else deal with high byte also.
; Point to WAIT/STOP opcode.
; Restore H register.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
105