MC68HC908GP20 Datasheet, PDF (375/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 0, setting the CHxMAX bit forces the duty
cycle of buffered and unbuffered PWM signals to 100%. As Figure 22-
13 shows, the CHxMAX bit takes effect in the cycle after it is set or
cleared. The output stays at the 100% duty cycle level until the cycle
after CHxMAX is cleared.
OVERFLOW
OVERFLOW
PTEx/TCHx
PERIOD
OVERFLOW
OVERFLOW OVERFLOW
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 22-13. CHxMAX Latency
22.10.6 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
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