MC68HC908GP20 Datasheet, PDF (324/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

BUS
CLOCK
WRITE
TO SPDR
INITIATION DELAY
MOSI
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
MSB
BIT 6
BIT 5
1
2
3
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
BUS
CLOCK
WRITE
TO SPDR
BUS
CLOCK
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 2;
2 POSSIBLE START POINTS
WRITE
LATEST
TO SPDR
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 8;
8 POSSIBLE START POINTS
LATEST
BUS
CLOCK
EARLIEST
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 32;
32 POSSIBLE START POINTS
LATEST
EARLIEST
SPSCK = INTERNAL CLOCK ÷ 128;
128 POSSIBLE START POINTS
LATEST
Figure 20-7. Transmission Start Delay (Master)
Advance Information
324
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor