MC68HC908GP20 Datasheet, PDF (272/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

PTY — Parity Bit
This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. (See Table 18-5.) Reset clears the PTY
bit.
1 = Odd parity
0 = Even parity
NOTE: Changing the PTY bit in the middle of a transmission or reception can
generate a parity error.
Table 18-5. Character Format Selection
Control Bits
M
PEN and
PTY
0
0X
1
0X
0
10
0
11
1
10
1
11
Start
Bits
1
1
1
1
1
1
Data
Bits
8
9
7
7
8
8
Character Format
Parity
Stop
Bits
None
1
None
1
Even
1
Odd
1
Even
1
Odd
1
Character
Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
18.9.2 SCI Control Register 2
SCI control register 2:
• Enables the following CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt
requests
– Enables the TC bit to generate transmitter CPU interrupt
requests
– Enables the SCRF bit to generate receiver CPU interrupt
requests
– Enables the IDLE bit to generate receiver CPU interrupt
requests
Advance Information
272
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor