MC68HC908GP20 Datasheet, PDF (173/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

11.5 Charge Pump
The internal FLASH charge pump is an analog circuit that provides the
proper voltage to the FLASH memory when reading, programming, and
erasing the memory arrays.
11.5.1 FLASH Charge Pump Frequency Control
The internal charge pump required for program, margin read, and erase
operations is designed to operate most efficiently with a 2 MHz clock.
The charge pump clock is derived from the bus clock. Table 11-1 shows
how the FDIV bits are used to select a charge pump frequency based on
the bus clock frequency. Program and erase operations cannot be
performed if the bus clock frequency is below 2 MHz.
.
FDIV1
0
0
1
1
Table 11-1. Charge Pump Clock Frequency
FDIV0
0
1
0
1
Pump Clock Frequency
Bus frequency ÷ 1
Bus frequency ÷ 2
Bus frequency ÷ 2
Bus frequency ÷ 4
Bus Clock Frequency
1.8 to 2.5 MHz
3.6 to 5.0 MHz
3.6 to 5.0 MHz
7.2 to 10.0 MHz
11.5.2 Voltage Regulator
The PMPSGVLVEN bit in the configuration register (CONFIG) enables
or disables the voltage regulator in the internal charge pump. For V_DD
greater than 3.6 V, the supply regulator must be enabled at all times for
the charge pump to supply the proper voltage to the FLASH memory.
For V_DD less than 3.6 V, the voltage regulator may be disabled to
conserve power. The charge pump no longer needs the voltage
regulator and can supply the proper voltage to the FLASH memory
without it. Leaving the voltage regulator enabled will not cause any harm.
The chip will merely consume more power than necessary. See
Section 8. Configuration Register (CONFIG).
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
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