MC68HC908GP20 Datasheet, PDF (209/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Table 15-1. Monitor Mode Signal Requirements and Options
IRQ
RESET
$FFFE/
$FFFF
PLL
PTC0
PTC1
PTC3
External
Clock⁽¹⁾
CGMOUT
Bus
Frequency
COP
For Serial
Communication
Baud
PTA0 PTA7 _{Rate(2) (3)}
Comment
X
GND
X
X
X
X
X
X
0
0
Disabled X
X
0
No operation until
reset goes high
V_TST
V_DD
or
V_TST
X
OFF 1
0
0
4.9152 4.9152
2.4576 Disabled 1
0
MHz
MHz
MHz
X
1
9600
DNA
PTC0 and PTC
voltages only
required if
IRQ = V_TST;
PTC3 determines
frequency divider
V_TST
V_DD
or
V_TST
X
OFF 1
0
1
9.8304 4.9152
2.4576 Disabled 1
0
MHz
MHz
MHz
X
1
9600
DNA
PTC0 and PTC1
voltages only
required if
IRQ = V_TST;
PTC3 determines
frequency divider
V_DD
V_DD
$0000 OFF X
X
X
9.8304 4.9152
2.4576 Disabled 1
0
MHz
MHz
MHz
X
1
9600
DNA
External frequency
always divided by 4
GND V_DD
$0000 ON X
X
X
32.768 4.9152
2.4576 Disabled 1
0
kHz
MHz
MHz
X
1
9600
DNA
PLL enabled
(BCS set)
in monitor code
V_DD
V_TST
$0000 OFF X
X
X
X
—
or
GND
—
Enabled X
X
—
Enters user
mode — will
encounter an illegal
address reset
V_DD
V_DD Non-zero OFF
X
X
X
X
—
or
or
GND V_TST
—
Enabled X
X
Notes:
1. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator
2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication
3. PTA7 = 0 → serial, PTA7 = 1 → parallel communication for security code entry
4. DNA = does not apply, X = don’t care
—
Enters user mode