MC68HC908GP20 Datasheet, PDF (291/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

19.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 19-3. This clock can
come from either an external oscillator or from the on-chip PLL. (See
Section 7. Clock Generator Module (CGMC).)
OSC2
OSC1
OSCILLATOR (OSC)
CGMXCLK
OSCSTOPENB
FROM
CONFIG
CGMRCLK
PHASE-LOCKED LOOP (PLL)
CGMOUT
SIMDIV2
TO TIMTB15A, ADC
SIM
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIMOSCEN
IT12
TO REST
OF CHIP
IT23
TO REST
OF CHIP
MONITOR MODE
USER MODE
PTC3
Figure 19-3. CGM Clock Signals
19.3.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See Section 12. External Interrupt (IRQ).
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
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