MC68HC908GP20 Datasheet, PDF (104/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = (When read) Break address match
0 = (When read) No break address match
6.6.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low
bytes of the desired breakpoint address. Reset clears the break address
registers.
Address: $FE09
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
Write:
9
Bit 8
Reset: 0
0
0
0
0
0
0
0
Figure 6-4. Break Address Register High (BRKH)
Address: $FE0A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 6-5. Break Address Register Low (BRKL)
Advance Information
104
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor