MC68HC908GP20 Datasheet, PDF (357/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Addr. Register Name
$0032
Read:
Timer 2 Channel 0
Register Low (T2CH0L)
Write:
Reset:
Timer 2 Channel 1 Status ^Read:
$0033
and Control Register Write:
(T2SC1) _Reset:
Bit 7
Bit 7
CH1F
0
0
6
6
CH1IE
0
5
4
3
2
5
4
3
2
Indeterminate after reset
0
MS1A ELS1B ELS1A
0
0
0
0
Read:
$0034
Timer 2 Channel 1
Register High (T2CH1H)
Write:
Bit 15
14
Reset:
13
12
11
10
Indeterminate after reset
Read:
$0035
Timer 2 Channel 1
Register Low (T2CH1L)
Write:
Bit 7
6
Reset:
5
4
3
2
Indeterminate after reset
= Unimplemented
Figure 22-2. TIM I/O Register Summary (Sheet 3 of 3)
1
Bit 0
1
Bit 0
TOV1 CH1MAX
0
0
9
Bit 8
1
Bit 0
22.5.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, TCLK. The prescaler generates seven clock rates from
the internal bus clock. The prescaler select bits, PS[2:0], in the TIM
status and control register select the TIM clock source.
22.5.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
357