MC68HC908GP20 Datasheet, PDF (181/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

11.9 FLASH Block Protect Register
The block protect register (FLBPR) is implemented as a byte within the
FLASH memory. Each bit, when programmed, protects a range of
addresses in the FLASH.
Address: $FF80
Bit 7
6
5
4
3
2
1
Read:
Bit 7
Bit 6
Bit 5
Bit 4 BPR3 BPR2 BPR1
Write:
Reset: U
U
U
U
U
U
U
U = Unaffected by reset. Initial value from factory is 0.
Figure 11-3. FLASH Block Protect Register (FLBPR)
Bit 0
BPR0
U
BPR3 — Block Protect Register Bit 3
This bit protects the memory contents in the address range $C000 to
$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR2 — Block Protect Register Bit 2
In a larger memory, this bit would protect the memory contents in the
address range $A000 to $FFFF. It is redundant in this implementation.
Setting this bit locks everything from $B000 to $FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR1 — Block Protect Register Bit 1
In a larger memory, this bit would protect the memory contents in the
address range $9000 to $FFFF. It is redundant in this implementation.
Setting this bit locks everything from $B000 to $FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
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