MC68HC908GP20 Datasheet, PDF (260/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

18.5.3.3 Data Sampling
The receiver samples the PTE1/RxD pin at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock is resynchronized at the
following times (see Figure 18-6):
• After every start bit
• After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.
PTE1/RxD
START BIT
LSB
SAMPLES
RT
CLOCK
RT CLOCK
STATE
RT CLOCK
RESET
START BIT
QUALIFICATION
START BIT
DATA
VERIFICATION SAMPLING
Figure 18-6. Receiver Data Sampling
Advance Information
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MC68HC908GP20 — Rev 2.1
Freescale Semiconductor