MC68HC908GP20 Datasheet, PDF (141/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

NOTE:
For V_DD > 3.6 V:
The voltage regular must always be enabled. The charge pump must
have the voltage regulator on to provide the proper voltage to the
FLASH memory.
For V_DD < 3.6 V:
The voltage regulator may be disabled to conserve power. The charge
pump does not use the voltage regulator when V_DD is less than 3.6 V,
so the voltage regulator can be turned off.
Leaving the voltage regulator enabled will not cuase any harm. The
chip will merely consume more power than necessary.
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
OSCSTOPENB enables the oscillator to continue operating during
stop mode. Setting the OSCSTOPENB bit allows the oscillator to
operate continuously even during stop mode. This is useful for driving
the timebase module to allow it to generate periodic wakeup while in
stop mode. (See 3.6 Clock Generator Module (CGM) subsection
3.6.2 Stop Mode.)
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
SCIBDSRC — SCI Baud Rate Clock Source Bit
SCIBDSRC controls the clock source used for the SCI. The setting of
this bit affects the frequency at which the SCI operates.
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 9. Computer Operating Properly (COP).)
1 = COP timeout period = 2¹³ – 2⁴ CGMXCLK cycles
0 = COP timeout period = 2¹⁸ – 2⁴ CGMXCLK cycles
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
141