MC68HC908GP20 Datasheet, PDF (385/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

23.9 3.0-V Control Timing
Characteristic⁽¹⁾
Frequency of operation⁽²⁾
Crystal option
External clock option⁽³⁾
Symbol
f_osc
Min
32
dc⁽⁴⁾
Max Unit
100 kHz
16.4 MHz
Internal operating frequency
f_op
—
4.1 MHz
Internal clock period (1/f_OP)
t_cyc
244
— ns
RESET input pulse width low⁽⁵⁾
t_IRL
125
— ns
IRQ interrupt pulse width low⁽⁶⁾
(edge-triggered)
t_ILIH
125
— ns
IRQ interrupt pulse period
16-bit timer⁽⁷⁾
Input capture pulse width
Input capture period
t_ILIL
t_TH,t_TL
t_TLTL
TBD Note 8
TBD
Note 8
—
t_cyc
— ns
—
t_cyc
Notes:
1. V_SS = 0 Vdc; timing shown with respect to 20% V_DD and 70% V_SS unless otherwise noted
2. See 23.17 Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation.
See appropriate table for this information.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse
width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
8. The minimum period, t_ILIL or t_TLTL, should not be less than the number of cycles it takes to
execute the interrrupt service routine plus t_CYC.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
385