MC68HC908GP20 Datasheet, PDF (114/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

to use as the source for the base clock. (See 7.4.8 Base Clock Selector
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
(See 7.7 Interrupts for information and precautions on using interrupts.)
The following conditions apply when the PLL is in automatic bandwidth
control mode:
• The ACQ bit (See 7.6.2 PLL Bandwidth Control Register.) is a
read-only indicator of the mode of the filter. (See 7.4.4
Acquisition and Tracking Modes.)
• The ACQ bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See 7.9 Acquisition/Lock Time
Specifications for more information.)
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See 7.9 Acquisition/Lock Time
Specifications for more information.)
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See 7.6.1 PLL
Control Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode
is used by systems that do not require an indicator of the lock condition
for proper operation. Such systems typically operate well below
f_BUSMAX.
Advance Information
114
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor