MC68HC908GP20 Datasheet, PDF (227/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
V_DD
DDRAx
PTAx
PTAPUEx
READ PTA ($0000)
INTERNAL
PULLUP
DEVICE
PTAx
Figure 16-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-2 summarizes
the operation of the port A pins.
Table 16-2. Port A Pin Functions
PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode
1
0
X⁽¹⁾
Input, V_DD(4)
0
0
X
Input, Hi-Z⁽²⁾
X
1
X
Output
NOTES:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to V_DD by internal pullup device
Accesses
to DDRA
Read/Write
DDRA7–DDRA0
DDRA7–DDRA0
DDRA7–DDRA0
Accesses to PTA
Read
Pin
Pin
PTA7–PTA0
Write
PTA7–PTA0⁽³⁾
PTA7–PTA0⁽³⁾
PTA7–PTA0
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
227