MC68HC908GP20 Datasheet, PDF (258/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

18.5.3 Receiver
Figure 18-5 shows the structure of the SCI receiver.
18.5.3.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).
18.5.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in
from the PTE1/RxD pin. The SCI data register (SCDR) is the read-only
buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character transfers to the SCDR. The SCI receiver full bit,
SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the
received byte can be read. If the SCI receive interrupt enable bit, SCRIE,
in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt
request.
Advance Information
258
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor