MC68HC908GP20 Datasheet, PDF (171/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

NOTE: A security feature prevents viewing of the FLASH contents.¹
11.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program, erase,
and margin read operations.
Address: $FE08
Bit 7
6
5
4
3
2
1
Bit 0
Read:
FDIV1
Write:
FDIV0
BLK1
BLK0 HVEN MARGIN ERASE PGM
Reset: 0
0
0
0
0
0
0
0
Figure 11-1. FLASH Control Register (FLCR)
FDIV1 — Frequency Divide Control Bit
This read/write bit together with FDIV0 selects the value by which the
charge pump clock is divided from the system clock. See 11.5.1
FLASH Charge Pump Frequency Control.
FDIV0 — Frequency Divide Control Bit
This read/write bit together with FDIV1 selects the value by which the
charge pump clock is divided from the system clock. See 11.5.1
FLASH Charge Pump Frequency Control.
BLK1— Block Erase Control Bit
This read/write bit together with BLK0 allows erasing of blocks of
varying size. See 11.6 FLASH Erase Operation for a description of
available block sizes.
BLK0 — Block Erase Control Bit
This read/write bit together with BLK1 allows erasing of blocks of
varying size. See 11.6 FLASH Erase Operation for a description of
available block sizes.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
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