MC68HC908GP20 Datasheet, PDF (201/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V_DD
LVIPWRD
FROM CONFIG
STOP INSTRUCTION
FROM CONFIG
LVIRSTD
LVISTOP
FROM CONFIG
LOW V_DD
DETECTOR
V_DD > LVI_Trip = 0
V_DD ≤ LVI_Trip = 1
LVI5OR3
FROM CONFIG
LVIOUT
LVI RESET
Figure 14-1. LVI Module Block Diagram
Addr. Register Name
Bit 7
6
5
4
3
2
Read: LVIOUT
0
0
0
0
0
$FE0C
LVI Status Register
(LVISR)
Write:
Reset: 0
0
0
0
0
0
= Unimplemented
Figure 14-2. LVI I/O Register Summary
1
Bit 0
0
0
0
0
14.4.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF level,
software can monitor V_DD by polling the LVIOUT bit. In the configuration
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
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