MC68HC908GP20 Datasheet, PDF (131/406 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

7.6.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming
information for the low byte of the modulo feedback divider.
Address: $0038
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MUL7
Write:
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
Reset: 0
1
0
0
0
0
0
0
Figure 7-7. PLL Multiplier Select Register Low (PMSL)
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback
divider that selects the VCO frequency multiplier, N. (See 7.4.3 PLL
Circuits and 7.4.6 Programming the PLL.) MUL7–MUL0 cannot be
written when the PLLON bit in the PCTL is set. A value of $0000 in the
multiplier select registers configures the modulo feedback divider the
same as a value of $0001. Reset initializes the register to $40 for a
default multiply value of 64.
NOTE: The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
MC68HC908GP20 — Rev 2.1
Freescale Semiconductor
Advance Information
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