HD64F3670 Datasheet, PDF (87/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

5.1.3 External Clock Input Method
Connect an external clock signal to pin OSC₁, and leave pin OSC₂ open. Figure 5.6 shows a typical
connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC₁
OSC ₂
Open
External clock input
Figure 5.6 Example of External Clock Input
5.2 Prescalers
5.2.1 Prescaler S
Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once
per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from
the reset state. In standby mode and subsleep mode, the system clock pulse generator stops.
Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S.
The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be
set separately for each on-chip peripheral function. In active mode and sleep mode, the clock input
to prescaler S is determined by the division factor designated by MA2 to MA0 in SYSCR2.
5.3 Usage Notes
5.3.1 Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Resonator circuit constants will differ
depending on the resonator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the resonator element
manufacturer. Design the circuit so that the resonator element never receives voltages exceeding
its maximum rating.
Rev. 2.0, 03/02, page 63 of 298