HD64F3670 Datasheet, PDF (210/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

13.6.1 Multiprocessor Serial Data Transmission
Figure 13.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same
as those in asynchronous mode.
Start transmission
[1]
Read TDRE flag in SSR
No
TDRE = 1
Yes
Set MPBT bit in SSR
Write transmit data to TDR
Yes
[2]
All data transmitted?
No
Read TEND flag in SSR
No
TEND = 1
Yes
No
[3]
Break output?
Yes
Clear PDR to 0 and set PCR to 1
[1] Read SSR and check that the TDRE
flag is set to 1, set the MPBT bit in
SSR to 0 or 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automatically
cleared to 0.
[2] To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
written to TDR, the TDRE flag is
automatically cleared to 0.
[3] To output a break in serial
transmission, set the port PCR to 1,
clear PDR to 0, then clear the TE bit
in SCR3 to 0.
Clear TE bit in SCR3 to 0
<End>
Figure 13.16 Sample Multiprocessor Serial Transmission Flowchart
Rev. 2.0, 03/02, page 186 of 298