HD64F3670 Datasheet, PDF (61/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Prior to executing BSET
Input/output
Pin state
PCR5
PDR5
P57
Input
Low
level
0
1
P56
Input
High
level
0
0
P55
Output
Low
level
1
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P50
Output
Low
level
1
0
BSET instruction executed
BSET #0, @PDR5
The BSET instruction is executed for port 5.
After executing BSET
Input/output
Pin state
PCR5
PDR5
P57
Input
Low
level
0
0
P56
Input
High
level
0
1
P55
Output
Low
level
1
0
P54
Output
Low
level
1
0
P53
Output
Low
level
1
0
P52
Output
Low
level
1
0
P51
Output
Low
level
1
0
P50
Output
High
level
1
1
Description on operation
When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
Finally, the CPU writes H'41 to PDR5, completing execution of BSET.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal.
However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy
of the PDR5 data in a work area in memory. Perform the bit manipulation on the data in the work
area, then write this data to PDR5.
Rev. 2.0, 03/02, page 37 of 298