HD64F3670 Datasheet, PDF (72/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.3 Reset Exception Handling
When the 5(6 pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-up, hold the 5(6 pin low until the clock pulse generator output
stabilizes. To reset the chip during operation, hold the 5(6 pin low for at least 10 system clock
cycles. When the 5(6 pin goes high after being held low for the necessary time, this LSI starts
reset exception handling. The reset exception handling sequence is shown in figure 3.1. The reset
exception handling sequence is as follows:
1. Set the I bit in the condition code register (CCR) to 1.
2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the
data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.
3.4 Interrupt Exception Handling
3.4.1 External Interrupts
There are external interrupts, NMI, IRQ3, IRQ0, and WKP.
NMI
NMI interrupt is requested by input falling edge to pin 10,.
NMI is the highest interrupt, and can always be accepted without depending on the I bit value
in CCR.
IRQ3 to IRQ0 Interrupts
IRQ3 to IRQ0 interrupts are requested by input signals to pins ,54 to ,54. These four
interrupts are given different vector addresses, and are detected individually by either rising
edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in
IEGR1.
When pins ,54 to ,54 are designated for interrupt input in PMR1 and the designated signal
edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.
When IRQ3 to IRQ0 interrupt is accepted, the I bit is set to 1 in CCR. These interrupts can be
masked by setting bits IEN3 to IEN0 in IENR1.
WKP5 to WKP0 Interrupts
WKP5 to WKP0 interrupts are requested by input signals to pins :.35 to :.30. These six
interrupts have the same vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in
IEGR2.
Rev. 2.0, 03/02, page 48 of 298