HD64F3670 Datasheet, PDF (81/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 4.1 Access and Data Bus Used
Word Access
Even Address Odd Address
ROM space
Upper 8 bits Lower 8 bits
RAM space
Upper 8 bits Lower 8 bits
I/O register with 8-bit data bus Upper 8 bits
width
Upper 8 bits
I/O register with 16-bit data Upper 8 bits
bus width
Lower 8 bits
Byte Access
Even Address Odd Address
Upper 8 bits Upper 8 bits
Upper 8 bits Upper 8 bits
Upper 8 bits Upper 8 bits
—
—
4.1.2 Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Bit Bit Name Initial Value
7 ABIF
0
6 ABIE
0
5 to 0 —
All 1
R/W Description
R/W Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
R/W Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
— Reserved
These bits are always read as 1.
4.1.3 Break Address Registers (BARH, BARL)
BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set
the first byte address of the instruction. The initial value of this register is H'FFFF.
4.1.4 Break Data Registers (BDRH, BDRL)
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, comparison data must be set in
BDRH for byte access. For word access, the data bus used depends on the address. See section
Rev. 2.0, 03/02, page 57 of 298