HD64F3670 Datasheet, PDF (289/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Instruction Mnemonic
Instruction
Fetch
I
Branch
Stack
Addr. Read Operation
J
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
SUBX
SUBX #xx:8, Rd
1
SUBX. Rs, Rd
1
TRAPA
TRAPA #xx:2
2
1
2
4
XOR
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XOR.W #xx:16, Rd
2
XOR.W Rs, Rd
1
XOR.L #xx:32, ERd
3
XOR.L ERs, ERd
2
XORC
Note:
XORC #xx:8, CCR
1
1. n:specified value in R4L and R4. The source and destination operands are accessed
n+1 times respectively.
2. Cannot be used in this LSI.
Rev. 2.0, 03/02, page 265 of 298