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HD64F3670 Datasheet, PDF (175/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer | |||
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Section 12 Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
The block diagram of the watchdog timer is shown in figure 12.1.
Internal
oscillator
ø
CLK
PSS
TCSRWD
TCWD
TMWD
Legend:
TCSRWD: Timer control/status register WD
TCWD: Timer counter WD
PSS:
Prescaler S
TMWD: Timer mode register WD
Internal reset
signal
Figure 12.1 Block Diagram of Watchdog Timer
12.1 Features
⢠Selectable from nine counter input clocks.
Eight clock sources (Ï/64, Ï/128, Ï/256, Ï/512, Ï/1024, Ï/2048, Ï/4096, and Ï/8192) or the
internal oscillator can be selected as the timer-counter clock. When the internal oscillator is
selected, it can operate as the watchdog timer in any operating mode.
⢠Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
12.2 Register Descriptions
The watchdog timer has the following registers.
⢠Timer control/status register WD (TCSRWD)
⢠Timer counter WD (TCWD)
⢠Timer mode register WD (TMWD)
WDT0110A_000020020300
Rev. 2.0, 03/02, page 151 of 298
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