HD64F3670 Datasheet, PDF (313/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Item
Page
5.1 System Clock
61
Generator
Figure 5.2 Block Diagram
of System Clock Generator
Revisions (See Manual for Details)
Added.
OSC2
Rev.
2.0
5.2.1 Prescaler S
6.1.1 System Control
Register 1 (SYSCR1)
6.1.4 Module Standby
Control Register 2
(MSTCR2)
Section 7 ROM
OSC1
LPM
LPM: Low-power mode (standby mode, subsleep mode)
63 Description amended.
2.0
In active mode and sleep mode, the clock input to
prescaler S is determined by the division factor
designated by MA2 to MA0 in SYSCR2.
66
2.0
Bit Bit Name Description
6
STS2
Standby Timer Select 2 to 0
5
STS1
These bits designate the time the
4
STS0
CPU and peripheral modules wait for
stable clock operation after exiting
from standby mode, to active mode or
sleep mode due to an interrupt. The
designation should be made
according to the clock frequency so
that the waiting time is at least 6.5 ms.
The relationship between the specified
value and the number of wait states is
shown in table 6.1. When an external
clock is to be used, the minimum
value (STS2 = STS1 = STS0 =1) is
recommended.
69 Deleted.
2.0
75 Description amended.
2.0
EIOT → E10T
• Reprogramming capability
The flash memory can be reprogrammed up to 1,000
times.
Description deleted.
• Power-down mode
Rev. 2.0, 03/02, page 289 of 298