HD64F3670 Datasheet, PDF (67/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.2 Register Descriptions
Interrupts are controlled by the following registers.
• Interrupt edge select register 1 (IEGR1)
• Interrupt edge select register 2 (IEGR2)
• Interrupt enable register 1 (IENR1)
• Interrupt flag register 1 (IRR1)
• Wakeup interrupt flag register (IWPR)
3.2.1 Interrupt Edge Select Register 1 (IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins and ,54 and
,54.
Bit Bit Name Initial Value R/W
7
0
−
6
1

5
1

4
1

3 IEG3
0
R/W
2
0

1
0

0 IEG0
0
R/W
Description
Reserved
This bit is always read as 0.
Reserved
These bits are always read as 1.
IRQ3 Edge Select
0: Falling edge of ,54 pin input is detected
1: Rising edge of ,54 pin input is detected
Reserved
These bits are always read as 0.
IRQ0 Edge Select
0: Falling edge of ,54 pin input is detected
1: Rising edge of ,54 pin input is detected
Rev. 2.0, 03/02, page 43 of 298