HD64F3670 Datasheet, PDF (315/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Item
7.4.1 Program/Program-
Verify
Figure 7.3
Program/Program-Verify
Flowchart
Page
84
Revisions (See Manual for Details)
Write pulse application subroutine
Apply Write Pulse
WDT enable
Set PSU bit in FLMCR1
*
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time=programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
Disable WDT
End Sub
START
Set SWE bit in FLMCR1
Wait 1 µs
Store 128-byte program data in program
data area and reprogram data area
n= 1
m= 0
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Apply Write pulse
Set PV bit in FLMCR1
Wait 4 µs
Set block start address as
verify address
H'FF dummy write to verify address
Wait 2 µs
*
Read verify data
7.4.3
87
Interrupt Handling when
Programming/Erasing
Flash Memory
Figure 7.4 Erase/Erase-
Verify Flowchart
Note: *The RTS instruction must not be used during the following 1. and 2. periods.
1. A period between 128-byte data programming to flash memory and the P bit clearing
2. A period between dummy writing of H'FF to a verify address and verify data reading
EV bit ← 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
*
Read verify data
Rev.
2.0
n←n+1
2.0
n←n+1
Note: *The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
9.5.1 Port Control Register 106
2.0
8 (PCR8)
Bit Bi Name Initial R/W Description
7
  Reserved
6

5

10.3.2 Time Constant
113 Initial value added.
2.0
Registers A and B
(TCORA, TCORB)
TCORA and TCORB are initialized to H'FF.
Rev. 2.0, 03/02, page 291 of 298