HD64F3670 Datasheet, PDF (234/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

16.1 Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Timer mode register W
Timer control register W
Timer interrupt enable register W
Timer status register W
Timer I/O control register 0
Timer I/O control register 1
Timer counter
General register A
General register B
General register C
General register D
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Flash memory enable register
Timer control register V0
Timer control/status register V
Timer constant register A
Timer constant register B
Timer counter V
Timer control register V1
Serial mode register
Bit rate register
Serial control register 3
Abbre-
Module
viation Bit No Address Name
TMRW 8
H'FF80 Timer W
TCRW 8
H'FF81 Timer W
TIERW 8
H'FF82 Timer W
TSRW 8
H'FF83 Timer W
TIOR0 8
H'FF84 Timer W
TIOR1 8
H'FF85 Timer W
TCNT 16 H'FF86 Timer W
GRA
16 H'FF88 Timer W
GRB
16 H'FF8A Timer W
GRC 16 H'FF8C Timer W
GRD 16 H'FF8E Timer W
FLMCR1 8
H'FF90 ROM
FLMCR2 8
H'FF91 ROM
EBR1 8
H'FF93 ROM
FENR 8
H'FF9B ROM
TCRV0 8
H'FFA0 Timer V
TCSRV 8
H'FFA1 Timer V
TCORA 8
H'FFA2 Timer V
TCORB 8
H'FFA3 Timer V
TCNTV 8
H'FFA4 Timer V
TCRV1 8
H'FFA5 Timer V
SMR
8
H'FFA8 SCI3
BRR
8
H'FFA9 SCI3
SCR3 8
H'FFAA SCI3
Data
Bus Access
Width State
8
2
8
2
8
2
8
2
8
2
8
2
16*¹ 2
16*¹ 2
16*¹ 2
16*¹ 2
16*¹ 2
8
2
8
2
8
2
8
2
8
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
Rev. 2.0, 03/02, page 210 of 298