HD64F3670 Datasheet, PDF (223/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

14.3.2 A/D Control/Status Register (ADCSR)
ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Bit Bit Name
7 ADF
Initial Value R/W
0
R/W
Description
A/D End Flag
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all the channels
selected in scan mode
6 ADIE
0
5 ADST
0
4 SCAN
0
3 CKS
0
[Clearing conditions]
• When 0 is written after reading ADF = 1
R/W A/D Interrupt Enable
A/D conversion end interrupt (ADI) request enabled
by ADF when 1 is set
R/W A/D Start
Setting this bit to 1 starts A/D conversion. In single
mode, this bit is cleared to 0 automatically when
conversion on the specified channel is complete. In
scan mode, conversion continues sequentially on
the specified channels until this bit is cleared to 0
by software, a reset, or a transition to standby
mode.
R/W Scan Mode
Selects single mode or scan mode as the A/D
conversion operating mode.
0: Single mode
1: Scan mode
R/W Clock Select
Selects the A/D conversions time
0: Conversion time = 134 states (max.)
1: Conversion time = 70 states (max.)
Clear the ADST bit to 0 before switching the
conversion time.
Rev. 2.0, 03/02, page 199 of 298