HD64F3670 Datasheet, PDF (69/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.2.3 Interrupt Enable Register 1 (IENR1)
IENR1 enables direct transition interrupts, and external pin interrupts.
Bit Bit Name Initial Value R/W Description
7 IENDT 0
R/W Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt requests
are enabled.
6
0

Reserved
This bit is always read as 0.
5 IENWP 0
R/W Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
:.3 to :.3. When the bit is set to 1, interrupt
requests are enabled.
4
1

Reserved
This bit is always read as 1.
3 IEN3
0
R/W IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the ,54 pin
are enabled.
2
0

Reserved
1
0

These bits are always read as 0.
0 IEN0
0
R/W IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the ,54 pin
are enabled.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always do so while interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handling for the interrupt will be executed after the clear
instruction has been executed.
Rev. 2.0, 03/02, page 45 of 298