HD64F3670 Datasheet, PDF (62/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Prior to executing BSET
MOV.B
MOV.B
MOV.B
#80, R0L
R0L, @RAM0
R0L, @PDR5
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
Input/output
Pin state
PCR5
PDR5
RAM0
P57
Input
Low
level
0
1
1
P56
Input
High
level
0
0
0
P55
Output
Low
level
1
0
0
P54
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
0
P51
Output
Low
level
1
0
0
P50
Output
Low
level
1
0
0
BSET instruction executed
BSET #0, @RAM0
The BSET instruction is executed designating the PDR5
work area (RAM0).
After executing BSET
MOV.B @RAM0, R0L
MOV.B R0L, @PDR5
The work area (RAM0) value is written to PDR5.
Input/output
Pin state
PCR5
PDR5
RAM0
P57
Input
Low
level
0
1
1
P56
Input
High
level
0
0
0
P55
Output
Low
level
1
0
0
P54
Output
Low
level
1
0
0
P53
Output
Low
level
1
0
0
P52
Output
Low
level
1
0
0
P51
Output
Low
level
1
0
0
P50
Output
High
level
1
1
1
Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
Rev. 2.0, 03/02, page 38 of 298