HD64F3670 Datasheet, PDF (85/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including a system
clock pulse generator. The system clock pulse generator consists of a system clock oscillator, a
duty correction circuit, and system clock dividers.
Figure 5.1 shows a block diagram of the clock pulse generators.
OSC₁
OSC₂
System
clock
oscillator
ø_OSC
(f_OSC)
Duty
correction
circuit
ø_OSC
(f_OSC)
System clock pulse generator
System
clock
divider
ø_OSC
ø_OSC/8
ø_OSC/16
ø_OSC/32
ø_OSC/64
ø
Prescaler S
(13 bits)
ø/2
to
ø/8192
Figure 5.1 Block Diagram of Clock Pulse Generators
The basic clock signals that drive the CPU and on-chip peripheral modules are ø.
The system clock is divided into ø/8192 to ø/2 by prescaler S and they are supplied to respective
peripheral modules.
5.1 System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system
clock generator.
OSC ₂
OSC ₁
LPM
LPM: Low-power mode (standby mode, subsleep mode)
Figure 5.2 Block Diagram of System Clock Generator
CPG0300A_000020020300
Rev. 2.0, 03/02, page 61 of 298