HD64F3670 Datasheet, PDF (18/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Figure 5.6 Example of External Clock Input ............................................................................ 63
Figure 5.7 Example of Incorrect Board Design......................................................................... 64
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ....................................................................................... 70
Section 7 ROM
Figure 7.1 Flash Memory Block Configuration ........................................................................ 76
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode........................... 82
Figure 7.3 Program/Program-Verify Flowchart ........................................................................ 84
Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................. 87
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration ......................................................................................... 91
Figure 9.2 Port 2 Pin Configuration ......................................................................................... 96
Figure 9.3 Port 5 Pin Configuration ......................................................................................... 98
Figure 9.4 Port 7 Pin Configuration ....................................................................................... 103
Figure 9.5 Port 8 Pin Configuration ....................................................................................... 106
Figure 9.6 Port B Pin Configuration....................................................................................... 109
Section 10 Timer V
Figure 10.1 Block Diagram of Timer V.................................................................................. 112
Figure 10.2 Increment Timing with Internal Clock ................................................................. 118
Figure 10.3 Increment Timing with External Clock ................................................................ 119
Figure 10.4 OVF Set Timing ................................................................................................. 119
Figure 10.5 CMFA and CMFB Set Timing ............................................................................ 119
Figure 10.6 TMOV Output Timing ........................................................................................ 120
Figure 10.7 Clear Timing by Compare Match ........................................................................ 120
Figure 10.8 Clear Timing by TMRIV Input............................................................................ 120
Figure 10.9 Pulse Output Example......................................................................................... 121
Figure 10.10 Example of Pulse Output Synchronized to TRGV Input..................................... 122
Figure 10.11 Contention between TCNTV Write and Clear.................................................... 123
Figure 10.12 Contention between TCORA Write and Compare Match ................................... 124
Figure 10.13 Internal Clock Switching and TCNTV Operation............................................... 124
Section 11 Timer W
Figure 11.1 Timer W Block Diagram..................................................................................... 127
Figure 11.2 Free-Running Counter Operation......................................................................... 136
Figure 11.3 Periodic Counter Operation ................................................................................. 137
Figure 11.4 0 and 1 Output Example (TOA = 0, TOB = 1) ..................................................... 137
Figure 11.5 Toggle Output Example (TOA = 0, TOB = 1)...................................................... 138
Figure 11.6 Toggle Output Example (TOA = 0, TOB = 1)...................................................... 138
Figure 11.7 Input Capture Operating Example ....................................................................... 139
Figure 11.8 Buffer Operation Example (Input Capture) .......................................................... 139
Figure 11.9 PWM Mode Example (1) .................................................................................... 140
Figure 11.10 PWM Mode Example (2) .................................................................................. 141
Rev. 2.0, 03/02, page xvi of xxii