HD64F3670 Datasheet, PDF (154/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit Bit Name Initial Value R/W Description
7 CCLR 0
R/W Counter Clear
The TCNT value is cleared by compare match A when this
bit is 1. When it is 0, TCNT operates as a free-running
counter.
6 CKS2 0
R/W Clock Select 2 to 0
5 CKS1 0
R/W Select the TCNT clock source.
4 CKS0 0
R/W 000: Internal clock: counts on φ
001: Internal clock: counts on φ/2
010: Internal clock: counts on φ/4
011: Internal clock: counts on φ/8
1XX: Counts on rising edges of the external event (FTCI)
When the internal clock source (φ) is selected, subclock
sources are counted in subactive and subsleep modes.
3 TOD 0
R/W Timer Output Level Setting D
0: Output value is 0*
1: Output value is 1*
2 TOC 0
R/W Timer Output Level Setting C
0: Output value is 0*
1: Output value is 1*
1 TOB
0
R/W Timer Output Level Setting B
0: Output value is 0*
1: Output value is 1*
0 TOA
0
R/W Timer Output Level Setting A
0: Output value is 0*
1: Output value is 1*
Legend X: Don't care.
Note: * The change of the setting is immediately reflected in the output value.
Rev. 2.0, 03/02, page 130 of 298