HD64F3670 Datasheet, PDF (83/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

When the address break is specified in the data read cycle
Register setting
• ABRKCR = H'A0
• BAR = H'025A
Program
0258 NOP
025A NOP
* 025C MOV.W @H'025A,R0
0260 NOP
Underline indicates the address
0262 NOP
to be stacked.
:
:
MOV MOV NOP MOV NOP Next
instruc- instruc- instruc- instruc- instruc- instru-
tion 1 tion 2 tion
tion
tion
ction Internal Stack
prefetch prefetch prefetch execution prefetch prefetch processing save
φ
Address
bus
Interrupt
request
025C 025E 0260 025A 0262
0264
Interrupt acceptance
SP-2
Figure 4.2 Address Break Interrupt Operation Example (2)
4.3 Usage Notes
When an address break is set to an instruction after a conditional branch instruction, and the
instruction set when the condition of the branch instruction is not satisfied is executed (see figure
4.3), note that an address break interrupt request is not generated. Therefore an address break must
not be set to the instruction after a conditional branch instruction.
[Register setting]
ABRKCR=H'80
BAR=H'0136
[Program]
012A
:
0134
*0136
0138
:
MOV.B . . .
:
BNE
NOP
NOP
:
BNE NOP MOV NOP
instruction instruction instruction instruction
prefetch prefetch prefetch prefetch
Adress bus
0134 0136 102A 0138
Adress break
interrupt request
Figure 4.3 Operation when Condition is not Satisfied in Branch Instruction
Rev. 2.0, 03/02, page 59 of 298