HD64F3670 Datasheet, PDF (163/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

TCNT value
H'FFFF
H'F000
H'AA55
H'55AA
H'1000
H'0000
FTIOA
GRA
H'1000
H'F000
Time
H'55AA
FTIOB
GRB
H'AA55
Figure 11.7 Input Capture Operating Example
Figure 11.8 shows an example of buffer operation when the GRA is set as an input-capture
register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter,
and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation,
the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
TCNT value
H'FFFF
H'DA91
H'5480
H'0245
H'0000
FTIOA
Time
GRA
GRC
H'0245
H'5480
H'0245
H'DA91
H'5480
Figure 11.8 Buffer Operation Example (Input Capture)
Rev. 2.0, 03/02, page 139 of 298