HD64F3670 Datasheet, PDF (155/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

11.3.3 Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Bit Bit Name Initial Value R/W
7 OVIE
0
R/W
6
1

5
1

4
1

3 IMIED
0
R/W
2 IMIEC
0
R/W
1 IMIEB
0
R/W
0 IMIEA
0
R/W
Description
Timer Overflow Interrupt Enable
When this bit is set to 1, FOVI interrupt requested by OVF
flag in TSRW is enabled.
Reserved
These bits are always read as 1.
Input Capture/Compare Match Interrupt Enable D
When this bit is set to 1, IMID interrupt requested by IMFD
flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable C
When this bit is set to 1, IMIC interrupt requested by IMFC
flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable B
When this bit is set to 1, IMIB interrupt requested by IMFB
flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable A
When this bit is set to 1, IMIA interrupt requested by IMFA
flag in TSRW is enabled.
11.3.4 Timer Status Register W (TSRW)
TSRW shows the status of interrupt requests.
Bit Bit Name Initial Value
7 OVF
0
6
1
5
1
4
1
R/W
R/W



Description
Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FFFF to H'0000
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
Reserved
These bits are always read as 1.
Rev. 2.0, 03/02, page 131 of 298