HD64F3670 Datasheet, PDF (71/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.2.5 Wakeup Interrupt Flag Register (IWPR)
IWPR is a status flag register for :.3 to :.3 interrupt requests.
Bit Bit Name Initial Value R/W Description
7
1
6
1

Reserved

These bits are always read as 1.
5 IWPF5 0
R/W WKP5 Interrupt Request Flag
[Setting condition]
When :.3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF5 is cleared by writing 0.
4 IWPF4 0
R/W WKP4 Interrupt Request Flag
[Setting condition]
When :.3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF4 is cleared by writing 0.
3 IWPF3 0
R/W WKP3 Interrupt Request Flag
[Setting condition]
When :.3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF3 is cleared by writing 0.
2 IWPF2 0
1 IWPF1 0
R/W WKP2 Interrupt Request Flag
[Setting condition]
When :.3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF2 is cleared by writing 0.
R/W WKP1 Interrupt Request Flag
[Setting condition]
When :.3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF1 is cleared by writing 0.
0 IWPF0 0
R/W WKP0 Interrupt Request Flag
[Setting condition]
When :.3 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF0 is cleared by writing 0.
Rev. 2.0, 03/02, page 47 of 298