HD64F3670 Datasheet, PDF (79/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Section 4 Address Break
The address break simplifies on-board program debugging. It requests an address break interrupt
when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR.
Break conditions that can be set include instruction execution at a specific address and a
combination of access and data at a specific address. With the address break function, the
execution start point of a program containing a bug is detected and execution is branched to the
correcting program. Figure 4.1 shows a block diagram of the address break.
Interrupt
generation
control circuit
Internal address bus
Comparator
BARH
BDRH
BARL
ABRKCR
ABRKSR
BDRL
Comparator
Legend:
BARH, BARL: Break address register
BDRH, BDRL: Break data register
ABRKCR: Address break control register
ABRKSR: Address break status register
Interrupt
Figure 4.1 Block Diagram of Address Break
4.1 Register Descriptions
Address break has the following registers.
• Address break control register (ABRKCR)
• Address break status register (ABRKSR)
• Break address register (BARH, BARL)
• Break data register (BDRH, BDRL)
ABK0001A_000020020300
Rev. 2.0, 03/02, page 55 of 298