HD64F3670 Datasheet, PDF (224/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit Bit Name
2 CH2
1 CH1
0 CH0
Initial Value R/W
0
R/W
0
R/W
0
R/W
Description
Channel Select 0 to 2
Select analog input channels.
When SCAN = 0
When SCAN = 1
000: AN0
000: AN0
001: AN1
001: AN0 to AN1
010: AN2
010: AN0 to AN2
011: AN3
011: AN0 to AN3
14.3.3 A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit Bit Name
7 TRGE
6 to —
1
0—
Initial Value R/W
0
R/W
All 1
—
0
R/W
Description
Trigger Enable
A/D conversion is started at the falling edge and
the rising edge of the external trigger signal
($'75*) when this bit is set to 1.
The selection between the falling edge and rising
edge of the external trigger pin ($'75*) conforms
to the WPEG5 bit in the interrupt edge select
register 2 (IEGR2)
Reserved
These bits are always read as 1.
Reserved
Do not set this bit to 1, though the bit is
readable/writable.
Rev. 2.0, 03/02, page 200 of 298