HD64F3670 Datasheet, PDF (109/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 7.4 Reprogram Data Computation Table
Program Data
0
0
1
1
Verify Data
0
1
0
1
Reprogram Data
1
0
1
1
Comments
Programming completed
Reprogram bit
—
Remains in erased state
Table 7.5 Additional-Program Data Computation Table
Reprogram Data
0
0
1
1
Verify Data
0
1
0
1
Additional-Program
Data
0
1
1
1
Comments
Additional-program bit
No additional programming
No additional programming
No additional programming
Table 7.6 Programming Time
n
Programming
(Number of Writes) Time
1 to 6
30
7 to 1,000
200
Note: Time shown in µs.
In Additional
Programming
10
—
Comments
7.4.2 Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR1). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
Rev. 2.0, 03/02, page 85 of 298