HD64F3670 Datasheet, PDF (214/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Serial
data
Start
bit
Receive
Stop Start
data (ID1) MPB bit bit
Receive data
Stop Mark state
(Data1) MPB bit (idle state)
1 0 D0 D1
D7 1 1 0 D0 D1
D7 0 1
1
1 frame
1 frame
MPIE
RDRF
RDR
value
LSI
operation
User
processing
ID1
RXI interrupt
request
MPIE cleared
to 0
RDRF flag
cleared
to 0
RDR data read
RXI interrupt request
is not generated, and
RDR retains its state
When data is not
this station's ID,
MPIE is set to 1
again
(a) When data does not match this receiver's ID
Serial
data
Start
bit
Receive
Stop Start
data (ID2) MPB bit bit
Receive data
Stop Mark state
(Data2) MPB bit (idle state)
1 0 D0 D1
D7 1 1 0 D0 D1
D7 0 1
1
1 frame
1 frame
MPIE
RDRF
RDR
ID1
value
ID2
Data2
LSI
operation
User
processing
RXI interrupt
request
MPIE cleared
to 0
RDRF flag
cleared
to 0
RDR data read
RXI interrupt RDRF flag
request
cleared
to 0
When data is
this station's
ID, reception
is continued
RDR data read
MPIE set to 1
again
(b) When data matches this receiver's ID
Figure 13.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Rev. 2.0, 03/02, page 190 of 298