HD64F3670 Datasheet, PDF (103/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

7.2.4 Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, and EBR1.
Bit Bit Name Initial Value R/W
7 FLSHE 0
R/W
6 to 0 —
All 0
—
Description
Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers cannot
be accessed when this bit is set to 0.
Reserved
These bits are always read as 0.
7.3 On-Board Programming Modes
There is a mode for programming/erasing of the flash memory; boot mode, which enables on-
board programming/erasing. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST
pin settings, 10, pin settings, and input level of each port, as shown in table 7.1. The input level
of each pin must be defined four states before the reset ends.
When changing to boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via SCI3. After erasing the entire flash memory, the programming control program is executed.
This can be used for programming initial values in the on-board state or for a forcible return when
programming/erasing can no longer be done in user program mode. In user program mode,
individual blocks can be erased and programmed by branching to the user program/erase control
program prepared by the user.
Table 7.1 Setting Programming Modes
TEST 10,
E10T_0 PB0
PB1
PB2
LSI State after Reset End
0
1
X
X
X
X
User Mode
0
0
1
X
X
X
Boot Mode
Legend: X: Don’t care.
Rev. 2.0, 03/02, page 79 of 298