HD64F3670 Datasheet, PDF (317/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Item
Page Revisions (See Manual for Details)
11.4.1 Normal Operation 137
Figure 11.6 Toggle Output
Example (TOA = 0,
TOB = 1)
TCNT value
H'FFFF
GRA
GRB
H'0000
Rev.
2.0
12.1 Features
151 Description amended.
2.0
• Selectable from nine counter input clocks.
Eight clock sources (φ/64, φ/128, φ/256, φ/512,
φ/1024, φ/2048, φ/4096, and φ/8192) or the internal
oscillator can be selected as the timer-counter clock.
When the internal oscillator is selected, it can operate
as the watchdog timer in any operating mode.
12.2.1 Timer
152 TCSRWD performs the TCSRWD and TCWD write 2.0
Control/Status Register
control. TCSRWD also controls the watchdog timer
WD (TCSRWD)
operation and indicates the operating state. TCSRWD
must be rewritten by using the MOV instruction. The
bit manipulation instruction cannot be used to change
the setting value.
Bit
R/W
7
R/W
5
R/W
3
R/W
1
R/W
13.3.4 Transmit Data
158 ^{Initial value added.}
2.0
Register (TDR)
TDR is initialized to H'FF.
13.3.7 Serial Status
163
2.0
Register (SSR)
Bit Bit Name
Initial Value
R/W
2
TEND
1
R
15.1 When Using Internal 207
Power Supply Step-Down
Circuit
15.2 When Not Using
208
Internal Power Supply
Step-Down Circuit
Description amended.
2.0
Connect the external power supply to the V_CC pin, and
connect a capacitance of approximately 0.1 µF
between V_CL and V_SS, as shown in figure 15.1.
Description amended.
2.0
When the internal power supply step-down circuit is
not used, connect the external power supply to the V_CL
pin and V_CC pin, as shown in figure 15.2.
Rev. 2.0, 03/02, page 293 of 298