HD64F3670 Datasheet, PDF (80/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

4.1.1 Address Break Control Register (ABRKCR)
ABRKCR sets address break conditions.
Bit Bit Name Initial Value
7 RTINTE 1
6 CSEL1 0
5 CSEL0 0
4 ACMP2 0
3 ACMP1 0
2 ACMP0 0
1 DCMP1 0
0 DCMP0 0
Legend: X: Don't care.
R/W Description
R/W RTE Interrupt Enable
When this bit is 0, the interrupt immediately after
executing RTE is masked and then one instruction must
be executed. When this bit is 1, the interrupt is not
masked.
R/W Condition Select 1 and 0
R/W These bits set address break conditions.
00: Instruction execution cycle
01: CPU data read cycle
10: CPU data write cycle
11: CPU data read/write cycle
R/W Address Compare Condition Select 2 to 0
R/W These bits comparison condition between the address set
R/W ^{in BAR and the internal address bus.}
000: Compares 16-bit addresses
001: Compares upper 12-bit addresses
010: Compares upper 8-bit addresses
011: Compares upper 4-bit addresses
1XX: Reserved (setting prohibited)
R/W Data Compare Condition Select 1 and 0
R/W These bits set the comparison condition between the data
set in BDR and the internal data bus.
00: No data comparison
01: Compares lower 8-bit data between BDRL and data
bus
10: Compares upper 8-bit data between BDRH and data
bus
11: Compares 16-bit data between BDR and data bus
When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 16.1,
Register Addresses.
Rev. 2.0, 03/02, page 56 of 298