HD64F3670 Datasheet, PDF (195/323 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

13.4.3 Data Transmission
Figure 13.5 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated.
Continuous transmission is possible because the TXI interrupt routine writes next transmit data
to TDR before transmission of the current transmit data has been completed.
3. The SCI3 checks the TDRE flag at the timing for sending the stop bit.
4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI
interrupt request is generated.
6. Figure 13.6 shows a sample flowchart for transmission in asynchronous mode.
Serial
data
Start
bit
Transmit Parity Stop Start
data
bit bit bit
Transmit
data
Parity Stop
bit bit
1 0 D0 D1
D7 0/1 1 0 D0 D1
D7 0/1 1
1 frame
1 frame
Mark
state
1
TDRE
TEND
LSI
TXI interrupt
operation request
User
generated
processing
TDRE flag
cleared to 0
Data written
to TDR
TXI interrupt request generated
TEI interrupt request
generated
Figure 13.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Rev. 2.0, 03/02, page 171 of 298